Nonvolatile memory devices include flash EEPROMs (electrical erasable programmable read only memory devices). FIG. 1 represents the relevant portion of a typical flash memory cell 10. The memory cell 10 typically includes a source region 12, a drain region 14 and a channel region 16 in a substrate 18; and a stacked gate structure 20 overlying the channel region 16. The stacked gate 20 includes a thin gate dielectric layer 22 (commonly referred to as the tunnel oxide) formed on the surface of the substrate 18. The stacked gate 20 also includes a polysilicon floating gate 24 which overlies the tunnel oxide 22 and an interpoly dielectric layer 26 which overlies the floating gate 24. The interpoly dielectric layer 26 is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers 26a and 26b sandwiching a nitride layer 26c. Lastly, a polysilicon control gate 28 overlies the interpoly dielectric layer 26. The channel region 16 of the memory cell 10 conducts current between the source region 12 and the drain region 14 in accordance with an electric field developed in the channel region 16 by the stacked gate structure 20.
The ONO interpoly dielectric layer has a number of important functions including insulating the control gate from the floating gate. However, high temperature processes such as a wet oxidation process and long processing times are associated with the fabrication of an ONO interpoly dielectric layer. High temperatures such as 950.degree. C. and above are undesirable because they tend to degrade polysilicon and/or tunnel oxide deleteriously increasing charge trapping. Specifically associated with forming the top oxide layer of an ONO interpoly dielectric layer using a wet oxidation process, an undesirably large amount of the nitride film may be consumed. Consequently, the resultant nitride layer is thinned which can cause charge leakage from the floating gate to the control gate. Another problem with forming the top oxide layer using a wet oxidation process is that it sometimes leads to junction problems at the nitride layer--top oxide layer interface. Long processing times makes the ONO interpoly dielectric layer fabrication process inefficient.
Even after an ONO interpoly dielectric layer is formed, there are a number of concerns. For example, if the top oxide layer is too thick, the required programming voltage increases undesirably. On the other hand, if the top oxide layer is too thin (for example, less than 10 .ANG.), charge retention time decreases undesirably since the charge tends to leak. If the nitride layer is too thin, charge leakage from the floating gate to the control gate may be caused, further decreasing charge retention time. Precisely controlling the thicknesses of the oxide layers and the nitride layer is a notable concern. Furthermore, it is difficult to provide three successive layers having uniform and even thickness on a consistent basis.
Using alternative dielectric layers in place of conventional ONO interpoly dielectric layers is known, such as tantalum oxide based interpoly dielectric layer, but these layers do not possess or exhibit the characteristics required of high quality interpoly dielectric layers in flash memory cells.
In view of the aforementioned concerns and problems, there is a need for flash memory cells of improved quality, particularly interpoly dielectric layers having improved quality, and more efficient methods of making such memory cells.